? semiconductor components industries, llc, 2010 april, 2010 ? rev. 6 1 publication order number: mje13007/d MJE13007G switchmode npn bipolar power transistor for switching power supply applications the MJE13007G is designed for high ? voltage, high ? speed power switching inductive circuits where fall time is critical. it is particularly suited for 115 and 220 v switchmode applications such as switching regulators, inverters, motor controls, solenoid/relay drivers and deflection circuits. features ? v ceo(sus) 400 v ? reverse bias soa with inductive loads @ t c = 100 c ? 700 v blocking capability ? soa and switching applications information ? standard to ? 220 ? these devices are pb ? free and are rohs compliant* maximum ratings rating symbol value unit collector ? emitter sustaining voltage v ceo 400 vdc collector ? base breakdown voltage v ces 700 vdc emitter ? base voltage v ebo 9.0 vdc collector current ? continuous ? peak (note 1) i c i cm 8.0 16 adc base current ? continuous ? peak (note 1) i b i bm 4.0 8.0 adc emitter current ? continuous ? peak (note 1) i e i em 12 24 adc total device dissipation @ t c = 25 c derate above 25 c p d 80 0.64 w w/ c operating and storage temperature t j , t stg ? 65 to 150 c thermal characteristics characteristics symbol max unit thermal resistance, junction ? to ? case r jc 1.56 c/w thermal resistance, junction ? to ? ambient r ja 62.5 c/w maximum lead temperature for soldering purposes 1/8 from case for 5 seconds t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. pulse test: pulse width = 5 ms, duty cycle 10%. *measurement made with thermocouple contacting the bottom insulated mounting surface of the package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied at a mounting torque of 6 to 8lbs. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. power transistor 8.0 amperes 400 volts ? 80 watts to ? 220ab case 221a ? 09 style 1 1 http://onsemi.com marking diagram 2 3 MJE13007G ay ww a = assembly location y = year ww = work week g = pb ? free package device package shipping ordering information MJE13007G to ? 220 (pb ? free) 50 units / rail
MJE13007G http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics (note 2) collector ? emitter sustaining voltage (i c = 10 ma, i b = 0) v ceo(sus) 400 ? ? vdc collector cutoff current (v ces = 700 vdc) (v ces = 700 vdc, t c = 125 c) i ces ? ? ? ? 0.1 1.0 madc emitter cutoff current (v eb = 9.0 vdc, i c = 0) i ebo ? ? 100 adc second breakdown second breakdown collector current with base forward biased i s/b see figure 6 clamped inductive soa with base reverse biased ? see figure 7 on characteristics (note 2) dc current gain (i c = 2.0 adc, v ce = 5.0 vdc) (i c = 5.0 adc, v ce = 5.0 vdc) h fe 8.0 5.0 ? ? 40 30 ? collector ? emitter saturation voltage (i c = 2.0 adc, i b = 0.4 adc) (i c = 5.0 adc, i b = 1.0 adc) (i c = 8.0 adc, i b = 2.0 adc) (i c = 5.0 adc, i b = 1.0 adc, t c = 100 c) v ce(sat) ? ? ? ? ? ? ? ? 1.0 2.0 3.0 3.0 vdc base ? emitter saturation voltage (i c = 2.0 adc, i b = 0.4 adc) (i c = 5.0 adc, i b = 1.0 adc) (i c = 5.0 adc, i b = 1.0 adc, t c = 100 c) v be(sat) ? ? ? ? ? ? 1.2 1.6 1.5 vdc dynamic characteristics current ? gain ? bandwidth product (i c = 500 madc, v ce = 10 vdc, f = 1.0 mhz) f t 4.0 14 ? mhz output capacitance (v cb = 10 vdc, i e = 0, f = 0.1 mhz) c ob ? 80 ? pf switching characteristics resistive load (table 1) delay time (v cc = 125 vdc, i c = 5.0 a, i b1 = i b2 = 1.0 a, t p = 25 s, duty cycle 1.0%) t d ? 0.025 0.1 s rise time t r ? 0.5 1.5 storage time t s ? 1.8 3.0 fall time t f ? 0.23 0.7 inductive load, clamped (table 1) voltage storage time v cc = 15 vdc, i c = 5.0 a t c = 25 c v clamp = 300 vdc t c = 100 c t sv ? ? 1.2 1.6 2.0 3.0 s crossover time i b(on) = 1.0 a, i b(off) = 2.5 a t c = 25 c l c = 200 ht c = 100 c t c ? ? 0.15 0.21 0.30 0.50 s fall time t c = 25 c t c = 100 c t fi ? ? 0.04 0.10 0.12 0.20 s 2. pulse test: pulse width 300 s, duty cycle 2.0%.
MJE13007G http://onsemi.com 3 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 i c , collector current (amps) v figure 1. base ? emitter saturation voltage 0.01 v i c , collector current (amps) figure 2. collector ? emitter saturation voltage 0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 5 10 i b , base current (amps) figure 3. collector saturation region v ce , collector-emitter voltage (volts) 0.01 0.1 1 10 h fe , dc current gain i c , collector current (amps) figure 4. dc current gain 0.1 1 10 100 1000 v r , reverse voltage (volts) figure 5. capacitance c, capacitance (pf) be(sat) , base-emitter saturation voltage (volts) ce(sat) , collector-emitter saturation voltage (volts) 1.4 1.2 1 0.8 0.6 0.4 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 3 2.5 2 1.5 1 0.5 0 100 10 1 10000 1000 100 10 0.02 0.05 0.1 0.2 0.5 1 2 5 10 i c /i b = 5 t c = - 40 c 25 c 100 c i c /i b = 5 t c = - 40 c 25 c 100 c t j = 25 c i c = 8 a i c = 5 a i c = 3 a i c = 1 a t j = 100 c 25 c 40 c v ce = 5 v c ib c ob t j = 25 c
MJE13007G http://onsemi.com 4 0.01 0.02 0.05 0.1 0.2 0.5 1 single pulse there are two limitations on the power handling ability of a transistor: average junc tion temperature and second breakdown. safe operating area curves indicate i c ? v ce limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. the data of figure 6 is based on t c = 25 c; t j(pk) is variable depending on power level. second breakdown pulse limits are valid for duty cycles to 10% but must be derated when t c 25 c. second breakdown limitations do not derate the same as thermal limitations. allowable current at the voltages shown on figure 6 may be found at any case temperature by using the a ppropriate curve on figure 8. at high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. use of reverse biased safe operating area data (figure 7) is discussed in the applications information section. 1000 10 20 30 70 100 200 50 300 500 v ce , collector-emitter voltage (volts) figure 6. maximum forward bias safe operating area i c , collector current (amps) 0 100 200 300 400 500 600 700 800 i c , collector current (amps) v cev , collector-emitter clamp voltage (volts) figure 7. maximum reverse bias switching safe operating area 20 40 60 80 100 120 140 160 t c , case temperature ( c) figure 8. forward bias power derating power derating factor 2 5 10 20 50 100 200 500 10k r(t), transient thermal resistance (normalized) t, time (msec) figure 9. typical thermal response for mje13007 20 10 5 1 0.5 0.02 0.05 0.2 0.1 2 100 50 0.01 10 8 6 4 2 0 1 0.8 0.6 0.4 0.2 0 1 0.01 0.02 0.05 0.1 0.2 0.5 0.07 0.7 extended soa @ 1 s, 10 s 10 s 1 s 1 ms 5 ms dc t c = 25 c bonding wire limit thermal limit second breakdown limit curves apply below rated v ceo t c 100 c gain 4 l c = 500 h v be(off) -5 v -2 v 0 v second breakdown derating thermal derating duty cycle, d = t 1 /t 2 t 1 p (pk) t 2 r jc (t) = r(t) r jc r jc = 1.56 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r jc (t) d = 0.5 d = 0.2 d = 0.1 d = 0.05 d = 0.02 d = 0.01
MJE13007G http://onsemi.com 5 specification information for switchmode applications introduction the primary considerations when selecting a power transistor for switchmode applications are voltage and current ratings, switching speed, and energy handling capability. in this section, these specifications will be discussed and related to the circuit examples illustrated in table 2. (note 1) voltage requirements both blocking voltage and sustaining voltage are important in switchmode applications. circuits b and c in table 2 illustrate applications that require high blocking voltage capability. in both circuits the switching transistor is subjected to voltages substantially higher than v cc after the device is completely off (see load line diagrams at i c = i leakage 0 in table 2). the blocking capability at this point depends on the base to emitter conditions and the device junction temperature. since the highest device capability occurs when the base to emitter junction is reverse biased (v cev ), this is the recommended and specified use condition. maximum i cev at rated v cev is specified at a relatively low reverse bias (1.5 volts) both at 25 c and 100 c. increasing the reverse bias will give some improvement in device blocking capability. the sustaining or active region voltage requirements in switching applications occur during turn ? on and turn ? off. if the load contains a significant capacitive component, high current and voltage can exist simultaneously during turn ? on and the pulsed forward bias soa curves (figure 6) are the proper design limits. for inductive loads, high voltage and current must be sustained simultaneously during turn ? off, in most cases, with the base to emitter junction reverse biased. under these conditions the collector voltage must be held to a safe level at or below a specific value of collector current. this can be accomplished by several means such as active clamping, rc snubbing, load line shaping, etc. the safe level for these devices is specified as a reverse bias safe operating area (figure 7) which represents voltage ? current conditions that can be sustained during reverse biased turn ? off. this rating is verified under clamped conditions so that the device is never subjected to an avalanche mode. note: 1. for detailed information on specific switching applications, see on semiconductor application note an719, an873, an875, an951.
MJE13007G http://onsemi.com 6 test waveforms t 1 adjusted to obtain i c test equipment scope tektronix 475 or equivalent t 1 l coil (i cm ) v cc l coil (i cm ) v clamp t 2 circuit values v cc = 125 v r c = 25 d1 = 1n5820 or equiv. test circuits reverse bias safe operating area and inductive switching resistive switching table 1. test conditions for dynamic performance l = 10 mh r b2 = 8 v cc = 20 volts i c(pk) = 100 ma l = 200 mh r b2 = 0 v cc = 15 volts r b1 selected for desired i b1 l = 500 mh r b2 = 0 v cc = 15 volts r b1 selected for desired i b1 v (br)ceo(sus) inductive switching rbsoa typical waveform s v cc l mur8100e v clamp = 300 vdc v ce 51 5.1 k tut i b i c +15 v +10v 50 r b1 r b2 150 500 f 1 f a 100 f v off common mtp8p10 mtp12n10 mpf930 mpf930 mtp8p10 mje210 i b mur105 1 f 3w 100 3w 150 3w +125 v scope r c tut d 1 r b -4 v i c v ce i cm t 1 t f t t v clamp t 2 time v cem t f clamped t f unclamped t 2 25 s +11 v 0 9 v t r , t f < 10 ns duty cycle = 1.0% r b and r c adjusted for desired i b and i c v ce v ce peak i b i b2 i b1
MJE13007G http://onsemi.com 7 voltage requirements (continued) in the four application examples (table 2) load lines are shown in relation to the pulsed forward and reverse biased soa curves. in circuits a and d, inductive reactance is clamped by the diodes shown. in circuits b and c the voltage is clamped by the output rectifiers, however, the voltage induced in the primary leakage inductance is not clamped by these diodes and could be large enough to destroy the device. a snubber network or an additional clamp may be required to keep the turn ? off load line within the reverse bias soa curve. load lines that fall within the pulsed forward biased soa curve during turn ? on and within the reverse bias soa curve during turn ? off are considered safe, with the following assumptions: 1. the device thermal limitations are not exceeded. 2. the turn ? on time does not exceed 10 s (see standard pulsed forward soa curves in figure 6). 3. the base drive conditions are within the specified limits shown on the reverse bias soa curve (figure 7). current requirements an efficient switching transistor must operate at the required current level with good fall time, high energy handling capability and low saturation voltage. on this data sheet, these parameters have been specified at 5.0 amperes which represents typical design conditions for these devices. the current drive requirements are usually dictated by the v ce(sat) specification because the maximum saturation voltage is specified at a forced gain condition which must be duplicated or exceeded in the application to control the saturation voltage. switching requirements in many switching applications, a major portion of the transistor power dissipation occurs during the fall time (t fi ). for this reason considerable effort is usually devoted to reducing the fall time. the recommended way to accomplish this is to reverse bias the base ? emitter junction during turn ? off. the reverse biased switching characteristics for inductive loads are shown in figures 12 and 13 and resistive loads in figures 10 and 11. usually the inductive load components will be the dominant factor in switchmode applications and the inductive switching data will more closely represent the device performance in actual application. the inductive switching characteristics are derived from the same circuit used to specify the reverse biased soa curves, (see table 1) providing correlation between test procedures and actual use conditions. switching time notes in resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage waveforms since they are in phase. however, for inductive loads which are common to switchmode power supplies and any coil driver, current and voltage waveforms are not in phase. therefore, separate measurements must be made on each waveform to determine the total switching time. for this reason, the following new terms have been defined. t sv = voltage storage time, 90% i b1 to 10% v clamp t rv = voltage rise time, 10 ? 90% v clamp t fi = current fall time, 90 ? 10% i c t ti = current tail, 10 ? 2% i c t c = crossover time, 10% v clamp to 10% i c an enlarged portion of the turn ? off waveforms is shown in figure 12 to aid in the visual identity of these terms. for the designer, there is minimal switching loss during storage time and the predominant switching power losses occur during the crossover interval and can be obtained using the standard equation from an222a: p swt = 1/2 v cc i c (t c ) f typical inductive switching times are shown in figure 13. in general, t rv + t fi ? t c . however, at lower test currents this relationship may not be valid. as is common with most switching transistors, resistive switching is specified at 25 c and has become a benchmark for designers. however, for designers of high frequency converter circuits, the user oriented specifications which make this a ?switchmode? transistor are the inductive switching speeds (t c and t sv ) which are guaranteed at 100 c.
MJE13007G http://onsemi.com 8 switching performance 12345678910 t, time (ns) i c , collector current (amp) figure 10. turn ? on time (resistive load) v cc = 125 v i c /i b = 5 i b(on) = i b(off) t j = 25 c pw = 25 s t, time (ns) 2345678910 i c , collector current (amp) figure 11. turn ? off time (resistive load) 1 t, time (ns) i c , collector current (amp) 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 figure 12. inductive switching measurements time figure 13. typical inductive switching times 10000 1000 100 10 10000 100 200 500 700 1000 2000 5000 7000 10000 10 20 50 100 200 500 1000 2000 5000 v cc = 125 v i c /i b = 5 i b(on) = i b(off) t j = 25 c pw = 25 s i c /i b = 5 i b(off) = i c /2 v clamp = 300 v l c = 200 h v cc = 15 v t j = 25 c t s t f t d t r t c t fi t sv i c i b v clamp 90% i b1 90% v clamp 90% i c v clamp 10% v clamp 10% i c 2% i c t sv t rv t fi t ti t c
MJE13007G http://onsemi.com 9 notes: see an569 for pulse power derating procedure. 1 1 1 notes: see an569 for pulse power derating procedure. 1 1 1 notes: see an569 for pulse power derating procedure. 1 1 1 2 2 2 notes: see an569 for pulse power derating procedure. 1 1 1 2 table 2. applications examples of switching circuits circuit load line diagrams time diagrams series switching regulator flyback inverter push ? pull inverter/converter solenoid driver a b c d v cc v o v cc v o n v cc v o solenoid v cc 16 a t c = 100 c 8 a turn-on turn-off v cc 400 v turn-on (forw ard bias) soa t on 10 s duty cycle 10% p d = 3200 w 300 v turn-off (reverse bias) soa 1.5 v v be(off) 9 v duty cycle 10% collector voltage collector current + 700 v t on t off time t i c t time v ce v cc t c = 100 c 16 a 8 a turn-on (forw ard bias) soa t on 10 s duty cycle 10% p d = 3200 w 300 v turn-off (reverse bias) soa 1.5 v v be(off) 9 v duty cycle 10% collector current turn-on turn-off 700 v 400 v v cc + n (v o ) + v cc v cc + n (v o ) + leakage spike collector voltage t t leakage spike v ce i c v cc + n (v o ) v cc t on t off 16 a 8 a turn-on turn-off + turn-on (forw ard bias) soa t on 10 s duty cycle 10% p d = 3200 w 300 v turn-off (reverse bias) soa 1.5 v v be(off) 9 v duty cycle 10% collector current 2 v cc 700 v 400 v v cc collector voltage t t t off t on v ce i c 2 v cc v cc t c = 100 c t c = 100 c turn-on (forw ard bias) soa t on 10 s duty cycle 10% p d = 3200 w 300 v turn-off (reverse bias) soa 1.5 v v be(off) 9 v duty cycle 10% 700 v 400 v 16 a 8 a + turn-off turn-on v cc collector voltage collector current i c t on t off t t v cc v ce
MJE13007G http://onsemi.com 10 package dimensions to ? 220ab case 221a ? 09 issue af style 1: pin 1. base 2. collector 3. emitter 4. collector notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.161 3.61 4.09 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.014 0.025 0.36 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane ? t ? c s t u r j on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mje13007/d switchmode is a trademark of semiconductor components industries, llc. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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